The present invention relates to an asynchronous signal processing circuit, and more particularly, to an asynchronous signal processing circuit in which an encoder, which carries out the analog-digital conversion in synchronism with a clock signal supplied together with an analog signal input, is integrally formed with a decoder, which executes the digital-analog conversion in synchronism with another clock signal supplied together with a digital signal input. Furthermore, a ladder voltage generator circuit is jointly used by said encoder and decoder, while a predetermined inhibit period is set up to coordinate the operation between said encoder and decoder at the time of changing over said ladder voltage generator circuit for use by said encoder or decoder.